The present invention relates to a program development support apparatus and, more particularly, to a program development support apparatus which supports debug of a computer program.
A program development support apparatus is especially used to develop and debug a program for operating a computer apparatus. Particularly, a program development support apparatus having a trace function is used to store an instruction address and instruction code of a CPU (Central Processing Unit), which generally change momentarily as a program is executed, in a memory called a trace memory and analyze them as a program execution result.
In recent years, programs installed in computer apparatuses are becoming complex and bulky, and a trace memory is required to have a large capacity to store a larger amount of execution result. On the other hand, since the operation speed of a CPU increases, a faster memory is necessary. Generally, a program development support apparatus having a trace function need be operated at the same speed as the operation frequency of the CPU. However, since a large-capacity, high-speed memory is very expensive, a decrease in amount of trace data to be stored in the trace memory has been required.
A technique that meets this requirement is disclosed in Japanese Patent Laid-Open No. 11-259335 (reference 1), in which the difference value between the immediately preceding program counter value and the current program counter value is recorded on the trace memory, and only for a branch instruction, the program counter value itself is recorded, thereby compressing the trace data. FIG. 12 shows the conventional program development support apparatus disclosed in reference 1.
Referring to FIG. 12, the program development support apparatus has an evaluation chip 301 prepared for program development and a tracer 302 for storing an instruction trace result. Instruction address/instruction code data output from a CPU 303 in the evaluation chip 301 is latched by an instruction address/instruction code latch circuit 321 in synchronism with a clock signal CLK, and a branch instruction determination circuit 323 determines whether the instruction is a branch instruction.
When the instruction is not a branch instruction, an instruction address data compression circuit 322 compresses the instruction address by generating the difference value between the immediately preceding program counter value and the current program counter value. A trace control circuit 324 combines compressed data of a plurality of instruction addresses into trace data in accordance with the bit width of a trace memory 306. The combined trace data is written in the trace memory 306. If the instruction is a branch instruction, the instruction address is directly written in the trace memory 306 without any compression.
In this prior art, since instruction addresses except those of branch instructions are compressed and stored in the trace memory, the capacity of the trace memory can be decreased. In addition, when compressed difference values are added starting from uncompressed data of the instruction address of a branch instruction, the instruction address can be reconstructed.
In the prior art shown in FIG. 12, however, only branch instructions are detected. If only a certain range of a program is to be repeatedly traced, as in, e.g., section trace, the original address cannot be reconstructed from compressed data. This is because the section trace start instruction address is not a branch instruction and is therefore compressed, like other instruction addresses.